[Verilog] 29. 4-bit CPU Project (2)
PC(Program Counter) 8bit Register↓ Code & Schematic더보기reg8.v'timescale 1ns / 1psmodule reg8( input [7:0] data_in, input inen, input oen, input clk, input clr, output [7:0] data_out ); reg [7:0] st; always @ (posedge clk or posedge clr) begin if (clr) st tb_reg8.v'timescale 1ns / 1psmodule tb_reg8();reg [7:0] data_in;reg inen;reg oen;reg clk;..
2024.08.28