[Verilog] 27. Counter

---

Counter

 

---

counter.v

`timescale 1ns / 1ps


module counter(
    input CLK,
    input RST,
    output reg [7:0] CNT
    );
    
    parameter FULL = 8'd255;
    parameter EMPTY = 8'b00;
    parameter ADD = 1;
    parameter SUBTRACT = 0;
    
    reg up_dn = 1;
    
    always @ (posedge CLK or negedge RST)
    begin
        if(RST) begin
        CNT <= 8'b00;
        up_dn <= 1;
        end
        
        else begin
            case (up_dn)
            ADD : begin            
            if(CNT >= FULL - 1) begin
                if(CNT == 8'd254)
                    CNT <= CNT + 1;
                up_dn <= SUBTRACT;   
                end 
            else
                CNT <= CNT + 1'b1;
            end
            
            SUBTRACT : begin
            if (CNT == EMPTY + 1) begin
                if(CNT == 8'd1)
                    CNT <= CNT - 1;
                up_dn <= ADD;
            end    
            else
                CNT <= CNT - 1'b1;
            end
            endcase
        end
    end
endmodule

 

 

 

---

Simulation

---

counter_tb.v

`timescale 1ns / 1ps
module counter_tb();

reg clk;
reg rst;
wire [7:0] Q;

parameter CLK_PD = 8.0;

counter uut0(
.CLK    (clk),
.RST    (rst),
.CNT    (Q)
);

always begin
    #(CLK_PD/2) clk = ~clk;
end

initial begin
    clk <= 0;
    rst <= 1'b1;
    #10;
    rst <= 1'b0;
end
endmodule

 

---

my_counter_tb.tcl

restart
add_force rst -radix hex {1 0ns} {0 5ns}
add_force clk -radix hex {1 0ns} {0 5ns} -repeat_every 10ns
run 6us

실행은

Tcl Console 창에

source + 주소 입력.