[Verilog] 15. AXI Write

 

---

AXI Write Operation

 

Write Operation Of AXI

Write Operation은 3개의 Channel로 이루어집니다. 

Handshake Of Write Operation

Handshake의 Source와 Destination이 Read동작과는 반대로 진행됩니다.

AXI Write Operation Pulse

Write Operation에 대한 순서를 잡아보겠습니다.

 

1) WADDR을 보내서 DATA 전송을 알립니다.

2) WADDR에 대한 Handshake 동작.(AWValid-AWRead)

3) WDATA를 보냅니다. 마지막 DATA에는 WLAST신호를 같이 보내 DATA Write가 끝났음을 알립니다.

4) WDATA에 대한 Handshake동작.(WValid-WRead)

5) BRESP를 보내 DATA 수신에 대해 응답합니다.

6) BRESP에 대한 Handshake동작.(BValid-BRead)

 

---

AXI Write Master

`timescale 1ns / 1ps

module axi_write_master(
    input           RST,
    input           CLK,
    input           START,
    input [4:0]     ADDR,
    input [7:0]    DATA,
    output [4:0]     AWADDR,
    output reg      AWVALID,
    input           AWREADY,
    output [7:0]    WDATA,
    output reg      WVALID,
    input           WREADY,
    input           BRESP,
    input           BVALID,
    output reg      BREADY,
    output reg      ERROR
    );

parameter   [1:0]   sidle = 2'b00,
                    saddr = 2'b01,
                    sdata = 2'b10,
                    sresp = 2'b11;
reg [1:0] cstate, nstate;

assign AWADDR = ADDR;
assign WDATA = DATA;

always @(posedge CLK)
    if(RST)
        cstate <= sidle;
    else
        cstate <= nstate;

always @(cstate, START, AWREADY, WREADY, BVALID)
begin
    AWVALID = 1'b0;
    WVALID = 1'b0;
    BREADY = 1'b0;
    case (cstate)
        sidle : begin
            if(START)
                nstate = saddr;
            else
                nstate = sidle;
        end
        saddr : begin
            AWVALID = 1'b1;
            if(AWREADY)
                nstate = sdata;
            else
                nstate = saddr;
        end
        sdata : begin
            WVALID = 1'b1;
            if(WREADY)
                nstate = sresp;
            else
                nstate = sdata;
        end
        sresp : begin
            BREADY = 1'b1;
            if(BVALID) begin
                ERROR = ~BRESP;
                nstate = sidle;
            end else
                nstate = sresp;
        end
        default : nstate = sidle;
    endcase                                                                                       
end     //always    
endmodule

 

---

AXI Write Slave

`timescale 1ns / 1ps


module axi_write_slave(
    input RST,
    input CLK,
    input [4:0] AWADDR,
    input AWVALID,
    output reg AWREADY,
    input [7:0] WDATA,
    input WVALID,
    output reg WREADY,
    output reg BRESP,
    output reg BVALID,
    input BREADY
    );

parameter   [2:0]   sidle = 3'd0,
                    saddr = 3'd1,
                    saw_chk = 3'd2,
                    sdata = 3'd3,
                    sw_chk = 3'd4,
                    sresp = 3'd5;

reg [2:0] cstate, nstate;                    

wire    [4:0]   addr;
wire    [7:0]   data;
wire            wea;
   
assign  addr = AWADDR;
assign  data = WDATA;
assign  wea = WVALID & WREADY;

RAM32x8 ram_0 (
  .clka         (CLK),    // input wire clka
  .wea          (wea),      // input wire [0 : 0] wea
  .addra        (addr),  // input wire [3 : 0] addra
  .dina         (data),    // input wire [7 : 0] dina
  .douta        ()  // output wire [31 : 0] douta
);    

always @(posedge CLK)
    if(RST)
        cstate <= sidle;
    else
        cstate <= nstate;

always @(cstate, AWVALID, WVALID, BREADY)
begin
    AWREADY = 1'b0;
    WREADY = 1'b0;
    BVALID = 1'b0;
    BRESP = 1'b0;
    
    case (cstate)
        sidle : begin
            if(AWVALID)
                nstate = saw_chk;
            else
                nstate = sidle;
        end
        saw_chk : begin
            AWREADY = 1'b1;
            nstate = sdata;
        end
        sdata : begin
            if(WVALID)
                nstate = sw_chk;
            else
                nstate = sdata;
        end
        sw_chk : begin
            WREADY = 1'b1;
            nstate = sresp;
        end
        sresp : begin
            BVALID = 1'b1;
            BRESP = 1'b1;
            if(BREADY)
                nstate = sidle;
            else
                nstate = sresp;
        end
        default : nstate = sidle;
    endcase                                                                                                                                
end     // always                
endmodule

---

AXI Write Testbench

`timescale 1ns / 1ps


module axi_write_tb();
parameter CLK_PD = 10.0;
reg rst, clk;
reg [4:0]   addr;
reg [7:0]   data;
reg         start;

wire [4:0]  awaddr;
wire [7:0]  wdata;
wire        awvalid, awready, wvalid, wready, bvalid, bready, bresp;
wire        error;

// uut instantiation
axi_write_master mst_0 (
    .RST        (rst),
    .CLK        (clk),
    .START      (start),
    .ADDR       (addr),
    .DATA       (data),
    .AWADDR     (awaddr),
    .AWVALID    (awvalid),
    .AWREADY    (awready),
    .WDATA      (wdata),
    .WVALID     (wvalid),
    .WREADY     (wready),
    .BRESP      (bresp),
    .BVALID     (bvalid),
    .BREADY     (bready),
    .ERROR      (error)
    );
axi_write_slave slv_0 (
    .RST        (rst),
    .CLK        (clk),
    .AWADDR     (awaddr),
    .AWVALID    (awvalid),
    .AWREADY    (awready),
    .WDATA      (wdata),
    .WVALID     (wvalid),
    .WREADY     (wready),
    .BRESP      (bresp),
    .BVALID     (bvalid),
    .BREADY     (bready)
    );    
// RESET, CLK gen
initial begin
    rst = 1'b1;
    #(CLK_PD*10);
    rst = 1'b0;
end
initial clk = 1'b0;
always #(CLK_PD/2) clk = ~clk;

//start, addr, data gen
integer i;

initial begin
    start = 1'b0;
    addr = 5'd0;
    data = 8'd0;
    wait (rst == 1'b0);
    repeat (5) @(posedge clk);
    
    for(i=0; i < 32; i= i+1) begin
        start = 1'b1;
        wait (bvalid);
        start = 1'b0;
        #(CLK_PD*3);
        addr = addr + 1;
        data = data + 1;
    end
    #(CLK_PD*20);
    $finish;
end                    
    
endmodule

AXI Simulation Pulse

Vitis AXI

[Vitis] 1. AXI