[Verilog] 9. RAM(Random Access Memory)

ROM(Read Only Memory)

RAM(Random Access Memory)

FIFO(First In First Out) = 선입 선출

my_ram.v

`timescale 1ns / 1ps

module my_ram(
    input RST,
    input CLK,
    input [3:0] ADDR,
    input [7:0] DIN,
    output reg [7:0] DOUT,
    input RW
    );
    
reg [7:0] mem [0:15];

always @ (posedge CLK) begin
        if (RST)
                DOUT <= 8'd0;                           // if reset is on, output is 0.
        else
                DOUT <= mem[ADDR];            // if reset is off, output is address
end
always @ (posedge CLK) begin
        if (RW == 1'b1)
                DOUT <= 8'd0;
end

//always @ (negedge RW) begin
//        DOUT <= 8'd0;
//        wait (mem[ADDR] == DIN);
//end

always @ (posedge CLK) begin
        if (RW == 1'b0)
                mem[ADDR] <= DIN;
end

 
endmodule

 

my_ram_tb.v

`timescale 1ns / 1ps

module my_ram_tb();
parameter CLK_PD = 8.0;
reg rst, clk, rw;
reg [3:0] addr;
reg [7:0] din;
wire [7:0] dout;
integer i;

my_ram uut0(
.RST    (rst),
.CLK    (clk),
.ADDR   (addr),
.DIN    (din),
.DOUT   (dout),
.RW     (rw)
    );

initial begin
    rst = 1'b1;
    #(CLK_PD*10);
    rst = 1'b0;
end

initial clk = 1'b0;
always #(CLK_PD/2) clk = ~clk;

initial begin
        addr = 4'd0;
        din = 8'd0;
        rw = 1'b1;
        wait (rst == 1'b0);
        #(CLK_PD * 20);
        rw = 1'b0;
        for (i = 0; i < 16; i = i +1) begin
                addr = i;
                din = i;
                #(CLK_PD);
        end
        #(CLK_PD * 20);
        rw = 1'b1;
        for (i = 0; i < 16; i = i +1) begin
                addr = i;
                #(CLK_PD);
        end
        
        #1000;
        $finish;
end

endmodule